The present disclosure relates generally to the field of semiconductor fabrication. In conventional practice, semiconductor fabrication begins with the provision of a semiconductor wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the semiconductor wafer are intended to support NMOS and PMOS semiconductor components. These regions are isolated from each other with the formation of electronically inert isolation trenches. Each region is then doped with a type of dopant opposite the electronic nature of the components to be created thereupon. The formation of the electronic components then occurs upon this semiconductor wafer, and typically involves doping the electronically active areas of the semiconductor wafer with the desired type of dopant. For instance, NMOS components are formed by implanting a p-type dopant in a region of the semiconductor, and then forming the components by implanting an n-type dopant in order to create the electronically active regions of the NMOS component. Each dopant is exposed to a thermal anneal, which restores the crystalline lattice structure of the semiconductor wafer (since the physical injection of ions can disrupt the crystalline lattice), and also electronically “activate” the dopant ions by positioning them within the same lattice structure. The components may then be connected through a metallization step, in which metal paths are formed to connect the electronically active areas of the components into a fully interconnected circuit.
It will be appreciated that the implantation of a dopant is a key step in semiconductor component fabrication. For many semiconductor components, the characteristics of doping, such as the choice of dopant, the implant method, and the resulting concentration and area of the dopant, dopant concentration vertical and lateral gradient, bear critically on the resulting performance and reliability of the components. One implant scenario that requires specific implanting is in the formation of source/drain regions of a MOSFET transistor. A typical transistor comprises two electronically active areas that serve as the source and drain regions of the transistor, which are bridged by a conductive gate. When the gate is powered above a certain threshold voltage, a conductive channel is formed between the source and drain regions to close the circuit; but when the gate is unpowered, the channel resists such electronic flow. In this context, the characteristics of the source/drain region doping bear directly on the threshold voltage of the gate and the resistance of the channel in powered and unpowered states. If the dopant concentration is too low or if the source and drain are too distant, the threshold voltage will be undesirably high. If the dopant concentration is too high or if the source and drain regions are too close, the threshold voltage will be undesirably low, and the resistance in the unpowered state may be insufficient to prevent electron flow. In this latter case, the effects that permit an undesired activation of the transistor are generally referred to as “short channel effects.”
One method of preventing short channel effects is by modifying the design of the source/drain regions to feature a source/drain extension region. In this design, the source and drain regions are deposited a small distance away from the gate structure, so that both regions feature a small gap exists between the electronically active region and the gate. This gap is then lightly and shallowly doped to form an “extension” of the electronically active region. In contrast with non-extended source/drain implants, these extensions serve as a comparatively thin and less conductive interface between the source/drain region and the gate, thereby desirably raising the threshold voltage of the gate and the resistance of the transistor channel while the gate is unpowered. The resulting transistor therefore exhibits higher predictability and enhanced performance.
The concepts described hereinabove are illustrated in FIG. 1, which presents a side-elevation view in section of a portion of a conventional semiconductor. In this figure, the semiconductor 10 comprises a silicon wafer 12, an area of which is designated to support either n-type or p-type electronic components. For an area intended to support NMOS components, the semiconductor substrate (an upper layer 14 of the silicon wafer 12) is doped with a p-type dopant, which will electronically insulate the NMOS components to be fabricated thereupon. Conversely, for an area intended to support PMOS components, the semiconductor substrate 14 is doped with an n-type dopant, which will electronically insulate the PMOS components to be fabricated thereupon. The area may also be electronically insulated from nearby structures by the formation of one or more isolation structures 16, such as a local oxidation of silicon (LOCOS) structure or an isolation trench. To form an electronic component like a transistor, the gate structure is first formed, comprising, in one common design, a thin layer of dielectric material 18 over which is formed a polysilicon layer 20. Next, areas 22 of the semiconductor substrate 14 on each side of the gate structures 18, 20 are lightly and shallowly doped with a dopant of the same type as the components to be formed (e.g., a p-type dopant for PMOS components, or an n-type dopant for NMOS components.) These lightly and shallowly doped areas 22 will function as the source/drain extension regions of the transistor. After this implantation, the semiconductor 10 is exposed to a high-temperature anneal, which “activates” the dopant ions implanted in the lightly-doped source/drain extension regions 22 by causing them to migrate into the crystalline structure of the silicon wafer 12, and also restores the regular lattice configuration of the silicon wafer 12 for consistent electronic flow. After this anneal, sidewall spacers 24 are formed over the sidewall spacer regions 22. The regions 26 of the semiconductor substrate 14 adjacent to the gate structures 18, 20 and the sidewall spacers 24 is then heavily doped with a dopant of the same type as the components to be formed. The regions 26 will function as the source and drain regions of the transistor. A second anneal step is then performed to activate the dopant ions implanted in the source/drain regions, for the reasons and according to the methods described hereinabove. The completion of these steps results in a functional NMOS or PMOS transistor.
In light of the foregoing explanation of source/drain extension regions and the impact of these designs on transistor performance, it will be appreciated that tight control over the depth of ion implantation and dopant concentration gradient is advantageous for semiconductor fabrication techniques. Such control is also desirable due to the trend of increasing miniaturization in electronic components, because shallower implant techniques may permit the use of thinner semiconductor wafers and the fabrication of smaller components. However, the source/drain extension regions must be designed not only to prevent electronic flow when the gate voltage is below the gate threshold, but also to permit electronic flow with low resistance when the gate voltage is above the gate threshold. This latter characteristic, known as sheet resistance, is a common metric of transistor performance.
It is always desirable to make further improvements in the area of semiconductor fabrication.